列挙型になっています
一応使っているので大きな間違いはないと思いますが
あまり使わないレジスタ(連続で読み出すようなところとか)は間違ってる可能性もあります
フツーのデバイスならアドレスが飛ぶってことも少ないので大丈夫だと思いますが
使う場合は各自確認してください
以下
ADT7420
L3G4200D
L3GD20
LIS331HH
LPS331AP
LSM303DLHC
LIS302DL
LSM9DS0 // 追加 2017/08/13
列挙型本体は続きに
enum ADT7420_register {
ADT7420_register_Temp_VAL_MOST = 0x00,
ADT7420_register_Temp_VAL_LEAST,
ADT7420_register_status,
ADT7420_register_configu,
ADT7420_register_THIGH_MOST,
ADT7420_register_THIGH_LEAST,
ADT7420_register_TLOW_MOST,
ADT7420_register_TLOW_LEAST,
ADT7420_register_TCRIT_MOST,
ADT7420_register_TCRIT_LEAST,
ADT7420_register_THYST,
ADT7420_register_ID,
ADT7420_register_SRESET = 0x2F,
};
enum L3G4200D_register {
L3G4200D_register_WHO_AM_I = 0x0F,
L3G4200D_register_CTRL_REG1 = 0x20,
L3G4200D_register_CTRL_REG2,
L3G4200D_register_CTRL_REG3,
L3G4200D_register_CTRL_REG4,
L3G4200D_register_CTRL_REG5,
L3G4200D_register_REFERENCE,
L3G4200D_register_OUT_TEMP,
L3G4200D_register_STATUS_REG,
L3G4200D_register_OUT_X_L,
L3G4200D_register_OUT_X_H,
L3G4200D_register_OUT_Y_L,
L3G4200D_register_OUT_Y_H,
L3G4200D_register_OUT_Z_L,
L3G4200D_register_OUT_Z_H,
L3G4200D_register_FIFO_CTRL_REG,
L3G4200D_register_FIFO_SRC_REG,
L3G4200D_register_INT1_CFG,
L3G4200D_register_INT1_SRC,
L3G4200D_register_INT1_TSH_XH,
L3G4200D_register_INT1_TSH_XL,
L3G4200D_register_INT1_TSH_YH,
L3G4200D_register_INT1_TSH_YL,
L3G4200D_register_INT1_TSH_ZH,
L3G4200D_register_INT1_TSH_ZL,
L3G4200D_register_INT1_DURATION,
};
enum L3GD20_register {
L3GD20_register_WHO_AM_I = 0x0F,
L3GD20_register_CTRL_REG1 = 0x20,
L3GD20_register_CTRL_REG2,
L3GD20_register_CTRL_REG3,
L3GD20_register_CTRL_REG4,
L3GD20_register_CTRL_REG5,
L3GD20_register_REFERENCE,
L3GD20_register_OUT_TEMP,
L3GD20_register_STATUS_REG,
L3GD20_register_OUT_X_L,
L3GD20_register_OUT_X_H,
L3GD20_register_OUT_Y_L,
L3GD20_register_OUT_Y_H,
L3GD20_register_OUT_Z_L,
L3GD20_register_OUT_Z_H,
L3GD20_register_FIFO_CTRL_REG,
L3GD20_register_FIFO_SRC_REG,
L3GD20_register_INT1_CFG,
L3GD20_register_INT1_SRC,
L3GD20_register_INT1_TSH_XH,
L3GD20_register_INT1_TSH_XL,
L3GD20_register_INT1_TSH_YH,
L3GD20_register_INT1_TSH_YL,
L3GD20_register_INT1_TSH_ZH,
L3GD20_register_INT1_TSH_ZL,
L3GD20_register_INT1_DURATION,
};
enum LIS331HH_register {
LIS331HH_register_CTRL_REG1 = 0x20,
LIS331HH_register_CTRL_REG2,
LIS331HH_register_CTRL_REG3,
LIS331HH_register_CTRL_REG4,
LIS331HH_register_CTRL_REG5,
LIS331HH_register_HP_FILTER_RESET,
LIS331HH_register_REFERENCE,
LIS331HH_register_STATUS_REG,
LIS331HH_register_OUT_X_L,
LIS331HH_register_OUT_X_H,
LIS331HH_register_OUT_Y_L,
LIS331HH_register_OUT_Y_H,
LIS331HH_register_OUT_Z_L,
LIS331HH_register_OUT_Z_H,
LIS331HH_register_INT1_CFG = 0x30,
LIS331HH_register_INT1_SOURCE,
LIS331HH_register_INT1_THS,
LIS331HH_register_INT1_DURATION,
LIS331HH_register_INT2_CFG,
LIS331HH_register_INT2_SOURCE,
LIS331HH_register_INT2_THS,
LIS331HH_register_INT2_DURATION,
};
enum LPS331AP_register {
LPS331AP_register_REF_P_XL = 0x08,
LPS331AP_register_REF_P_L,
LPS331AP_register_REF_P_H,
LPS331AP_register_WHO_AM_I = 0x0F,
LPS331AP_register_RES_CONF,
LPS331AP_register_CTRL_REG1 = 0x20,
LPS331AP_register_CTRL_REG2,
LPS331AP_register_CTRL_REG3,
LPS331AP_register_INT_CFG_REG,
LPS331AP_register_INT_SOURCE_REG,
LPS331AP_register_IHS_P_LOW_REG,
LPS331AP_register_IHS_P_HIGH_REG,
LPS331AP_register_STATUS_REG,
LPS331AP_register_PRESS_POUT_XL_REH,
LPS331AP_register_PRESS_OUT_L,
LPS331AP_register_PRESS_OUT_H,
LPS331AP_register_TEMP_OUT_L,
LPS331AP_register_TEMP_OUT_H,
LPS331AP_register_AMP_CTRL = 0x30,
};
enum LSM303LDHC_register {
LSM303DLHC_register_CTRL_REG1_A = 0x20,
LSM303DLHC_register_CTRL_REG2_A,
LSM303DLHC_register_CTRL_REG3_A,
LSM303DLHC_register_CTRL_REG4_A,
LSM303DLHC_register_CTRL_REG5_A,
LSM303DLHC_register_CTRL_REG6_A,
LSM303DLHC_register_REFERENCE_A,
LSM303DLHC_register_STATUS_REG_A,
LSM303DLHC_register_OUT_X_L_A,
LSM303DLHC_register_OUT_X_H_A,
LSM303DLHC_register_OUT_Y_L_A,
LSM303DLHC_register_OUT_Y_H_A,
LSM303DLHC_register_OUT_Z_L_A,
LSM303DLHC_register_OUT_Z_H_A,
LSM303DLHC_register_FIFO_CTRL_REG_A,
LSM303DLHC_register_FIFO_SRC_REG_A,
LSM303DLHC_register_INT1_CFG_A,
LSM303DLHC_register_INT1_SOURCE_A,
LSM303DLHC_register_INT1_THS_A,
LSM303DLHC_register_INT1_DURATION_A,
LSM303DLHC_register_INT2_CFG_A,
LSM303DLHC_register_INT2_SOURCE_A,
LSM303DLHC_register_INT2_THS_A,
LSM303DLHC_register_INT2_DURATION_A,
LSM303DLHC_register_CLICK_CFG_A,
LSM303DLHC_register_CLICK_SRC_A,
LSM303DLHC_register_CLICK_THS_A,
LSM303DLHC_register_TIME_LIMIT_A,
LSM303DLHC_register_TIME_LATENCY_A,
LSM303DLHC_register_TIME_WINDWO_A,
LSM303DLHC_register_CRA_REG_M = 0x00,
LSM303DLHC_register_CRB_REG_M,
LSM303DLHC_register_MR_REG_M,
LSM303DLHC_register_OUT_X_H_M,
LSM303DLHC_register_OUT_X_L_M,
LSM303DLHC_register_OUT_Z_H_M,
LSM303DLHC_register_OUT_Z_L_M,
LSM303DLHC_register_OUT_Y_H_M,
LSM303DLHC_register_OUT_Y_L_M,
LSM303DLHC_register_SR_REG_M,
LSM303DLHC_register_IRA_REG_M,
LSM303DLHC_register_IRB_REG_M,
LSM303DLHC_register_IRC_REG_M,
LSM303DLHC_register_TEMP_OUT_H_M = 0x31,
LSM303DLHC_register_TEMP_OUT_L_M,
}
enum LIS302DL_register {
LIS302DL_register_WHO_AM_I = 0x0F, /* r */
LIS302DL_register_CTRL_REG1 = 0x20, /* rw */
LIS302DL_register_CTRL_REG2, /* rw */
LIS302DL_register_CTRL_REG3, /* rw */
LIS302DL_register_HP_FILTER_RESET, /* r */
LIS302DL_register_STATUS_REG = 0x27, /* r */
LIS302DL_register_OUT_X = 0x29, /* r */
LIS302DL_register_OUT_Y = 0x2B, /* r */
LIS302DL_register_OUT_Z = 0x2D, /* r */
LIS302DL_register_FF_WU_CFG_1 = 0x30, /* rw */
LIS302DL_register_FF_WU_SRC_1, /* r */
LIS302DL_register_FF_WU_THS_1, /* rw */
LIS302DL_register_FF_WU_DURATION_1, /* rw */
LIS302DL_register_FF_WU_CFG_2, /* rw */
LIS302DL_register_FF_WU_SRC_2, /* r */
LIS302DL_register_FF_WU_THS_2, /* rw */
LIS302DL_register_FF_WU_DURATION_2, /* rw */
LIS302DL_register_CLICK_CFG, /* rw */
LIS302DL_register_CLICK_SRC, /* r */
LIS302DL_register_CLICK_THSY_X = 0x3B, /* rw */
LIS302DL_register_CLICK_THSZ, /* rw */
LIS302DL_register_CLICK_TIME_LIMIT, /* rw */
LIS302DL_register_CLICK_LATENCY, /* rw */
LIS302DL_register_CLICK_WINDOW, /* rw */
}; /* */
enum LSM9DS0_register
{
LSM9DS0_register_WHO_AM_I_G = 0x0F,
LSM9DS0_register_CTRL_REG1_G = 0x20,
LSM9DS0_register_CTRL_REG2_G,
LSM9DS0_register_CTRL_REG3_G,
LSM9DS0_register_CTRL_REG4_G,
LSM9DS0_register_CTRL_REG5_G,
LSM9DS0_register_REFERENCE_G,
LSM9DS0_register_STATUS_REG_G = 0x27,
LSM9DS0_register_OUT_X_L_G,
LSM9DS0_register_OUT_X_H_G,
LSM9DS0_register_OUT_Y_L_G,
LSM9DS0_register_OUT_Y_H_G,
LSM9DS0_register_OUT_Z_L_G,
LSM9DS0_register_OUT_Z_H_G,
LSM9DS0_register_FIFO_CTRL_REG_G,
LSM9DS0_register_FIFO_SRC_REG_G,
LSM9DS0_register_INT1_CFG_G,
LSM9DS0_register_INT1_SRC_G,
LSM9DS0_register_INT1_TSH_XH_G,
LSM9DS0_register_INT1_TSH_XL_G,
LSM9DS0_register_INT1_TSH_YH_G,
LSM9DS0_register_INT1_TSH_YL_G,
LSM9DS0_register_INT1_TSH_ZH_G,
LSM9DS0_register_INT1_TSH_ZL_G,
LSM9DS0_register_INT1_DURATION_G,
LSM9DS0_register_OUT_TEMP_L_XM = 0x05,
LSM9DS0_register_OUT_TEMP_H_XM,
LSM9DS0_register_STATUS_REG_M,
LSM9DS0_register_OUT_X_L_M,
LSM9DS0_register_OUT_X_H_M,
LSM9DS0_register_OUT_Y_L_M,
LSM9DS0_register_OUT_Y_H_M,
LSM9DS0_register_OUT_Z_L_M,
LSM9DS0_register_OUT_Z_H_M,
LSM9DS0_register_WHO_AM_I_XM = 0x0F,
LSM9DS0_register_INT_CTRL_REG_M = 0x12,
LSM9DS0_register_INT_SRC_REG_M,
LSM9DS0_register_INT_THS_L_M,
LSM9DS0_register_INT_THS_H_M,
LSM9DS0_register_OFFSET_X_L_M,
LSM9DS0_register_OFFSET_X_H_M,
LSM9DS0_register_OFFSET_Y_L_M,
LSM9DS0_register_OFFSET_Y_H_M,
LSM9DS0_register_OFFSET_Z_L_M,
LSM9DS0_register_OFFSET_Z_H_M,
LSM9DS0_register_REFERENCE_X,
LSM9DS0_register_REFERENCE_Y,
LSM9DS0_register_REFERENCE_Z,
LSM9DS0_register_CTRL_REG0_XM,
LSM9DS0_register_CTRL_REG1_XM,
LSM9DS0_register_CTRL_REG2_XM,
LSM9DS0_register_CTRL_REG3_XM,
LSM9DS0_register_CTRL_REG4_XM,
LSM9DS0_register_CTRL_REG5_XM,
LSM9DS0_register_CTRL_REG6_XM,
LSM9DS0_register_CTRL_REG7_XM,
LSM9DS0_register_STATUS_REG_A,
LSM9DS0_register_OUT_X_L_A,
LSM9DS0_register_OUT_X_H_A,
LSM9DS0_register_OUT_Y_L_A,
LSM9DS0_register_OUT_Y_H_A,
LSM9DS0_register_OUT_Z_L_A,
LSM9DS0_register_OUT_Z_H_A,
LSM9DS0_register_FIFO_CTRL_REG,
LSM9DS0_register_FIFO_SRC_REG,
LSM9DS0_register_INT_GEN_1_REG,
LSM9DS0_register_INT_GEN_1_SRC,
LSM9DS0_register_INT_GEN_1_THS,
LSM9DS0_register_INT_GEN_1_DURATION,
LSM9DS0_register_INT_GEN_2_REG,
LSM9DS0_register_INT_GEN_2_SRC,
LSM9DS0_register_INT_GEN_2_THS,
LSM9DS0_register_INT_GEN_2_DURATION,
LSM9DS0_register_CLICK_CFG,
LSM9DS0_register_CLICK_SRC,
LSM9DS0_register_CLICK_THS,
LSM9DS0_register_TIME_LIMIT,
LSM9DS0_register_TIME_LATENCY,
LSM9DS0_register_TIME_WINDOW,
LSM9DS0_register_Act_THS,
LSM9DS0_register_Act_DUR,
};
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